1. Field
The present invention provides a method and apparatus for integrating a frequency-locked loop (“FLL”) filter in polar transmitters.
2. Description of Related Art
Radio frequency (“RF”) communication systems receive data in analog form. The received data is then converted to digital form prior to processing. On the transmission side, the digital data is converted to analog form and broadcasted through the RF communication system. Transmitting signals requires synthesizing many different frequencies, typically using a small number of reference frequencies. A phase-locked loop (“PLL”) is used for this purpose.
A conventional PLL consists generally of three parts: a reference frequency input portion, a loop filter portion and a voltage-controlled oscillator (“VCO”) portion. The reference frequency input portion includes a phase comparator and may include a frequency divider (which may be programmable). The phase comparator compares an output signal of the PLL with the reference frequency itself or the reference frequency divided down, thereby producing an error signal. The loop filter filters the error signal to produce a control signal that is applied to the VCO. During operation, the control signal drives the VCO in the proper direction so as to cause the error signal to be driven to zero or nearly zero.
PLLs generally operate in two different modes: an acquisition mode during which the PLL locks onto a particular frequency, and a tracking mode during which the PLL ensures that it remains locked. Both fast acquisition and accurate tracking are important design objectives. Unfortunately, these design objectives are generally conflicting. For fast acquisition, a wide loop bandwidth is desired. For accurate tracking, in the presence of modulation, a narrow loop bandwidth is desired. The disparity between the desired bandwidths in the two modes may be considerable.
For example, in cellular applications when changing channels, a wide loop bandwidth is desired to accomplish the frequency change as quickly as possible. When operating on a single channel, voice data having low frequency content is modulated onto a carrier signal. The PLL attempts in effect to cancel the modulation, which appears to the PLL as frequency drift. To accomplish slow modulation, therefore, a very narrow loop bandwidth is desired, such that the modulation is accomplished outside the PLL bandwidth.
Two-point modulation addresses this problem by providing a slow path and a fast path. The slow path has a low-pass response which sets the center frequency of the VCO. The fast path typically comprises a digital-to-analog converter (“DAC”) and a low-pass filter which allows the baseband modulation to go through. However, conventional two-point modulation systems fail to provide an accurate control signal to the VCO because of the offset inherent in the digital-to-analog conversion devices.
In addition, the loop filter of a PLL circuit is composed of capacitive elements and resistive elements that are not part of the integrated circuits (“ICs”). This is because capacitive elements with requisite capacitance consume a large footprint on the IC. Decreasing the capacitance footprint requires increasing the resistances of the resistive elements. However, such approach increases the thermal noise created by the resistive elements.
In the PLL circuit, the voltage from the loop filter is directly applied to the control terminal of the VCO. Therefore, if the thermal noise of the passive elements, which define the loop filter, and external noise intrusion are high and the control sensitivity of the VCO is high, this will deteriorate VCO output phase noise.
Therefore, there is a need for an improved method and apparatus to provide center frequency and baseband modulation signal to the VCO substantially free of noise while forming the entire circuit on an a small, integrated, solid state semiconductor device.